A system-on-chip (SoC) is an integrated circuit that integrates various components of a computer or other electronic system fabricated on a single die (e.g., silicon die). An SoC can include digital, analog, mixed-signal, and even radio-frequency functions on a single die. SoC digital circuits can include both standard and custom logic circuits (e.g., processors), as well as memory circuits. SoCs can also include digital circuits dedicated to testing and/or verifying the functionality of other portions of the SoC, commonly known as built-in self-test (BIST).
The density and/or feature size of the memories being fabricated is rapidly increasing particularly as compared to SoC logic circuits. Additionally, the portion of an SoC comprising embedded memories is increasing, and can occupy a significant portion of a design. The smaller feature size and increasing portion of an SoC occupied by memories also can result in an increase in potential faults or defects and, consequently, a reduction in SoC yield due to the embedded memories. In the context of these larger SoC designs with more memory, the conventional approach of Direct Memory Access (DMA) for memory testing can be costly in terms of silicon area, routing complexity, and test time. Accordingly, memory built-in self-test (MBIST) has become an attractive alternative and can offer benefits such as high fault coverage with reasonable trade-offs in terms of area, complexity, and test time.
Conventionally, MBIST comprises a variety of pre-established algorithms that can be executed by one or more controllers added to the SoC design for that purpose. Conventionally, MBIST controllers have been designed to execute pre-established algorithms in a pre-specified sequence during SoC manufacturing test. In addition, based on the type of memories and the tests that need to be applied to them, an SoC design can comprise multiple MBIST controllers, each assigned to test one or more of the memories comprising the SoC. For example, in an SoC with 200 memories, 25 controllers can be assigned to test these memories, with each controller responsible for managing the tests of 4-10 memories. Due to optimizations for cost, size, etc., such controllers conventionally have been non-programmable such that their algorithms and targeted fault models cannot be changed after the chip has been manufactured.
Nevertheless, it is possible for new or improved algorithms to be developed for further improvements in, e.g., coverage, speed, reliability, etc. after a chip has been manufactured. To enable testing an already-manufactured chip using such new or improved algorithms, field programmable MBIST (PMBIST) can be utilized. In this approach, the MBIST algorithms can be loaded into a programmable memory and executed by the PMBIST controller, similar to the manner in which modified or updated versions of executable software can be loaded into a computer-readable memory for execution by a processor. A PMBIST controller can provide the capability to apply certain classes and/or variations of algorithms and to change the algorithms that can be applied. For example, a PMBIST controller can allow modification of a test algorithm at run-time simply modifying the test program.
This approach can provide various advantages. For example, during the ramp-up period of a manufacturing process, a designer can determine the defects that are escaping the applied tests, modify existing algorithms or introduce new algorithms to target those defects, and change the test program at run time to catch them. In addition, it can be difficult to predict all types of defects that can manifest themselves during a manufacturing process, so a designer can modify the test algorithms as these become more familiar. Furthermore, an SoC and its revisions can have a design life long enough to be manufactured with different fabrication technologies (e.g., different feature sizes). A certain test suite that was effective and/or efficient for a particular technology when the SoC was originally designed may be unsatisfactory when the SoC design is migrated to a newer technology. Under such circumstances, additional algorithms may need to be applied to detect defects related to the newer technology. In this manner, a PMBIST controller can be re-used across different design revisions or even different designs.
Several issues and/or problems can arise during the development and/or configuration of PMBIST hardware for an SoC design. In the development process for an SoC that includes both hardware (e.g., logic and memory circuits) and software, the hardware is usually created first so that the software can be written based on a known hardware interface. As such, it can be preferable or necessary to develop and/or configure the PMBIST hardware early in the design process. However, a single SoC design can utilize various types of memories that are provided by different memory vendors, each of which can utilize a different memory model. This variety of memory types and models makes early development and/or configuration of comprehensive PMBIST difficult. In addition, the design flow in the electronic design automation (EDA) tool used for PMBIST insertion into the SoC design can be interrupted due to errors in the memory models or the tool itself, causing delay in the PMBIST hardware and, consequently, the software that is dependent on the hardware design.
Accordingly, it can be beneficial to address at least some of these issues and/or problems with improved data structures and design flows for PMBIST development, configuration, and insertion into SoC designs.